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hwacc_vmx.h File Reference


Detailed Description

HWACCM - VMX Structures and Definitions. (VMM)

Definition in file hwacc_vmx.h.

#include <VBox/types.h>
#include <VBox/err.h>
#include <VBox/x86.h>
#include <iprt/assert.h>

Go to the source code of this file.

Classes

struct  EPTPD
union  EPTPDE
struct  EPTPDE2MBITS
struct  EPTPDEBITS
struct  EPTPDPT
union  EPTPDPTE
struct  EPTPDPTEBITS
struct  EPTPML4
union  EPTPML4E
struct  EPTPML4EBITS
struct  EPTPT
union  EPTPTE
struct  EPTPTEBITS
union  VMX_CAPABILITY
struct  VMXMSR

VMX EPT paging structures

#define EPT_PD_MASK   X86_PD_PAE_MASK
#define EPT_PD_SHIFT   X86_PD_PAE_SHIFT
#define EPT_PDE2M_PG_MASK   ( 0x000fffffffe00000ULL )
#define EPT_PDE_PG_MASK   X86_PDE_PAE_PG_MASK_FULL
#define EPT_PDPT_MASK   X86_PDPT_MASK_AMD64
#define EPT_PDPT_SHIFT   X86_PDPT_SHIFT
#define EPT_PDPTE_PG_MASK   X86_PDPE_PG_MASK_FULL
#define EPT_PG_ENTRIES   X86_PG_PAE_ENTRIES
#define EPT_PML4_MASK   X86_PML4_MASK
#define EPT_PML4_SHIFT   X86_PML4_SHIFT
#define EPT_PML4E_PG_MASK   X86_PML4E_PG_MASK_FULL
#define EPT_PT_MASK   X86_PT_PAE_MASK
#define EPT_PT_SHIFT   X86_PT_PAE_SHIFT
#define EPT_PTE_PG_MASK   X86_PTE_PAE_PG_MASK_FULL
enum  VMX_FLUSH {
  VMX_FLUSH_PAGE = 0, VMX_FLUSH_SINGLE_CONTEXT = 1, VMX_FLUSH_ALL_CONTEXTS = 2, VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
  VMX_FLUSH_32BIT_HACK = 0x7fffffff
}
typedef const EPTPDPCEPTPD
typedef const EPTPDEPCEPTPDE
typedef const EPTPDPTPCEPTPDPT
typedef const EPTPDPTEPCEPTPDPTE
typedef const EPTPML4PCEPTPML4
typedef const EPTPML4EPCEPTPML4E
typedef const EPTPTPCEPTPT
typedef const EPTPTEPCEPTPTE
typedef EPTPDPEPTPD
typedef EPTPDEPEPTPDE
typedef EPTPDPTPEPTPDPT
typedef EPTPDPTEPEPTPDPTE
typedef EPTPML4PEPTPML4
typedef EPTPML4EPEPTPML4E
typedef EPTPTPEPTPT
typedef EPTPTEPEPTPTE
 AssertCompileSize (EPTPTE, 8)
 AssertCompileSize (EPTPTEBITS, 8)
 AssertCompileSize (EPTPDE, 8)
 AssertCompileSize (EPTPDE2MBITS, 8)
 AssertCompileSize (EPTPDEBITS, 8)
 AssertCompileSize (EPTPDPTE, 8)
 AssertCompileSize (EPTPDPTEBITS, 8)
 AssertCompileSize (EPTPML4E, 8)
 AssertCompileSize (EPTPML4EBITS, 8)

Defines

#define VMXReadVMCS   VMXReadVMCS32
#define VMXWriteVMCS   VMXWriteVMCS32
#define VMXWriteVMCS64(idxField, u64Val)   VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
VMX MSRs - Basic VMX information.
#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a)   ((a >> 49ULL) & 1)
#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a)   (a & 0x7FFFFFFF)
#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a)   ((a >> 50ULL) & 0xF)
#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a)   ((a >> 48ULL) & 1)
#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a)   ((a >> 32ULL) & 0xFFF)
MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
#define MSR_IA32_VMX_EPT_CAPS_EMT_UC   RT_BIT_64(8)
#define MSR_IA32_VMX_EPT_CAPS_EMT_WB   RT_BIT_64(14)
#define MSR_IA32_VMX_EPT_CAPS_EMT_WC   RT_BIT_64(9)
#define MSR_IA32_VMX_EPT_CAPS_EMT_WP   RT_BIT_64(13)
#define MSR_IA32_VMX_EPT_CAPS_EMT_WT   RT_BIT_64(12)
#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS   RT_BIT_64(3)
#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS   RT_BIT_64(4)
#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS   RT_BIT_64(5)
#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS   RT_BIT_64(6)
#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS   RT_BIT_64(7)
#define MSR_IA32_VMX_EPT_CAPS_INVEPT   RT_BIT_64(20)
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL   RT_BIT_64(26)
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT   RT_BIT_64(25)
#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV   RT_BIT_64(24)
#define MSR_IA32_VMX_EPT_CAPS_INVVPID   RT_BIT_64(32)
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL   RT_BIT_64(42)
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT   RT_BIT_64(41)
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL   RT_BIT_64(43)
#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV   RT_BIT_64(40)
#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY   RT_BIT_64(1)
#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY   RT_BIT_64(2)
#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY   RT_BIT_64(0)
#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS   RT_BIT_64(16)
#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS   RT_BIT_64(17)
#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS   RT_BIT_64(18)
#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS   RT_BIT_64(19)
VMX MSRs - Misc VMX info.
#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a)   ((a >> 6ULL) & 0x7)
#define MSR_IA32_VMX_MISC_CR3_TARGET(a)   ((a >> 16ULL) & 0x1FF)
#define MSR_IA32_VMX_MISC_MAX_MSR(a)   ((((a >> 25ULL) & 0x7) + 1) * 512)
#define MSR_IA32_VMX_MISC_MSEG_ID(a)   (a >> 32ULL)
#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a)   (a & 0x1f)
VMX MSRs - VMCS enumeration field info
#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a)   ((a >> 1ULL) & 0x1FF)
VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY   3
#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH   2
#define VMX_APIC_ACCESS_TYPE_LINEAR_READ   0
#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE   1
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY   10
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR   15
VMX_VMCS_GUEST_ACTIVITY_STATE
#define VMX_CMS_GUEST_ACTIVITY_ACTIVE   0x0
#define VMX_CMS_GUEST_ACTIVITY_HLT   0x1
#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN   0x2
#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT   0x3
VMX Basic Exit Reasons.
#define VMX_EFLAGS_RESERVED_0   (~0xffc08028)
#define VMX_EFLAGS_RESERVED_1   0x00000002
Extended Page Table Pointer (EPTP)
#define VMX_EPT_MEMTYPE_UC   0
#define VMX_EPT_MEMTYPE_WB   6
#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT   3
#define VMX_EPT_PAGE_WALK_LENGTH_MASK   7
#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT   3
VM Instruction Errors
#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND   28
#define VMX_ERROR_VMCALL   1
#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION   22
#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR   24
#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS   20
#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS   19
#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR   2
#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR   3
#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR   18
#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS   7
#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE   8
#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL   25
#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR   16
#define VMX_ERROR_VMENTRY_MOV_SS   26
#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS   17
#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS   4
#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR   9
#define VMX_ERROR_VMPTRLD_VMXON_PTR   10
#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION   11
#define VMX_ERROR_VMREAD_INVALID_COMPONENT   12
#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS   6
#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS   5
#define VMX_ERROR_VMWRITE_INVALID_COMPONENT   VMX_ERROR_VMREAD_INVALID_COMPONENT
#define VMX_ERROR_VMWRITE_READONLY_COMPONENT   13
#define VMX_ERROR_VMXOFF_DUAL_MONITOR   23
#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP   15
VMX Basic Exit Reasons.
#define VMX_EXIT_APIC_ACCESS   44
#define VMX_EXIT_CPUID   10
#define VMX_EXIT_CRX_MOVE   28
#define VMX_EXIT_DRX_MOVE   29
#define VMX_EXIT_EPT_MISCONFIG   49
#define VMX_EXIT_EPT_VIOLATION   48
#define VMX_EXIT_ERR_INVALID_GUEST_STATE   33
#define VMX_EXIT_ERR_MACHINE_CHECK   41
#define VMX_EXIT_ERR_MSR_LOAD   34
#define VMX_EXIT_EXCEPTION   0
#define VMX_EXIT_EXTERNAL_IRQ   1
#define VMX_EXIT_HLT   12
#define VMX_EXIT_INIT_SIGNAL   3
#define VMX_EXIT_INVALID   -1
#define VMX_EXIT_INVD   13
#define VMX_EXIT_INVEPT   50
#define VMX_EXIT_INVPG   14
#define VMX_EXIT_INVVPID   53
#define VMX_EXIT_IO_SMI_IRQ   5
#define VMX_EXIT_IRQ_WINDOW   7
#define VMX_EXIT_MONITOR   39
#define VMX_EXIT_MWAIT   36
#define VMX_EXIT_PAUSE   40
#define VMX_EXIT_PORT_IO   30
#define VMX_EXIT_PREEMPTION_TIMER   52
#define VMX_EXIT_RDMSR   31
#define VMX_EXIT_RDPMC   15
#define VMX_EXIT_RDTSC   16
#define VMX_EXIT_RSM   17
#define VMX_EXIT_SIPI   4
#define VMX_EXIT_SMI_IRQ   6
#define VMX_EXIT_TASK_SWITCH   9
#define VMX_EXIT_TPR   43
#define VMX_EXIT_TR_ACCESS   47
#define VMX_EXIT_TRIPLE_FAULT   2
#define VMX_EXIT_VMCALL   18
#define VMX_EXIT_VMCLEAR   19
#define VMX_EXIT_VMLAUNCH   20
#define VMX_EXIT_VMPTRLD   21
#define VMX_EXIT_VMPTRST   22
#define VMX_EXIT_VMREAD   23
#define VMX_EXIT_VMRESUME   24
#define VMX_EXIT_VMWRITE   25
#define VMX_EXIT_VMXOFF   26
#define VMX_EXIT_VMXON   27
#define VMX_EXIT_WBINVD   54
#define VMX_EXIT_WRMSR   32
#define VMX_EXIT_XDTR_ACCESS   46
#define VMX_EXIT_XSETBV   55
VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a)   (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID   RT_BIT(11)
#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a)   (a & RT_BIT(12))
#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a)   ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT   8
#define VMX_EXIT_INTERRUPTION_INFO_VALID(a)   (a & RT_BIT(31))
#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT   31
#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a)   (a & 0xff)
#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a)   (a & ~RT_BIT(12))
VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT   5
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT   0
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT   3
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI   2
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW   4
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT   6
VMX_EXIT_APIC_ACCESS
#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a)   (a & 0xfff)
#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a)   ((a >> 12) & 0xf)
CRx accesses
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a)   ((a >> 4) & 3)
#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a)   ((a >> 8) & 0xF)
#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a)   ((a >> 16) & 0xFFFF)
#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a)   ((a >> 6) & 1)
#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a)   (a & 0xF)
#define VMX_EXIT_QUALIFICATION_CRX_RES1(a)   ((a >> 7) & 1)
#define VMX_EXIT_QUALIFICATION_CRX_RES2(a)   ((a >> 12) & 0xF)
VMX_EXIT_QUALIFICATION_CRX_ACCESS
Rest: reserved.

#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS   2
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW   3
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ   1
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE   0
VMX_VMCS_RO_EXIT_QUALIFICATION
#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a)   ((a >> 4) & 1)
#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a)   ((a >> 8) & 0xF)
#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a)   (a & 7)
#define VMX_EXIT_QUALIFICATION_DRX_RES1(a)   ((a >> 3) & 1)
#define VMX_EXIT_QUALIFICATION_DRX_RES2(a)   ((a >> 5) & 7)
VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
Rest: reserved.

#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ   1
#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE   0
VMX_EXIT_EPT_VIOLATION
#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ   RT_BIT(0)
#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE   RT_BIT(1)
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE   RT_BIT(5)
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT   RT_BIT(3)
#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE   RT_BIT(4)
#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID   RT_BIT(7)
#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH   RT_BIT(2)
#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS   RT_BIT(8)
VMX_EXIT_PORT_IO
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a)   ((a >> 3) & 1)
#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a)   ((a >> 6) & 1)
#define VMX_EXIT_QUALIFICATION_IO_PORT(a)   ((a >> 16) & 0xffff)
#define VMX_EXIT_QUALIFICATION_IO_REP(a)   ((a >> 5) & 1)
#define VMX_EXIT_QUALIFICATION_IO_STRING(a)   ((a >> 4) & 1)
#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a)   (a & 7)
VMX_EXIT_QUALIFICATION_IO_DIRECTION
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN   1
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT   0
VMX_EXIT_QUALIFICATION_IO_ENCODING
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX   0
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM   1
VMX_EXIT_QUALIFICATION_TASK_SWITCH
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a)   (a & 0xffff)
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a)   ((a >> 30)& 0x3)
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL   0
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT   3
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET   1
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP   2
VMCS field encoding - 16 bits guest fields
#define VMX_VMCS16_GUEST_FIELD_CS   0x802
#define VMX_VMCS16_GUEST_FIELD_DS   0x806
#define VMX_VMCS16_GUEST_FIELD_ES   0x800
#define VMX_VMCS16_GUEST_FIELD_FS   0x808
#define VMX_VMCS16_GUEST_FIELD_GS   0x80A
#define VMX_VMCS16_GUEST_FIELD_LDTR   0x80C
#define VMX_VMCS16_GUEST_FIELD_SS   0x804
#define VMX_VMCS16_GUEST_FIELD_TR   0x80E
#define VMX_VMCS16_GUEST_FIELD_VPID   0x0
VMCS field encoding - 16 bits host fields
#define VMX_VMCS16_HOST_FIELD_CS   0xC02
#define VMX_VMCS16_HOST_FIELD_DS   0xC06
#define VMX_VMCS16_HOST_FIELD_ES   0xC00
#define VMX_VMCS16_HOST_FIELD_FS   0xC08
#define VMX_VMCS16_HOST_FIELD_GS   0xC0A
#define VMX_VMCS16_HOST_FIELD_SS   0xC04
#define VMX_VMCS16_HOST_FIELD_TR   0xC0C
VMCS field encoding - 32 Bits guest state fields
#define VMX_VMCS32_GUEST_ACTIVITY_STATE   0x4826
#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS   0x4816
#define VMX_VMCS32_GUEST_CS_LIMIT   0x4802
#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS   0x481A
#define VMX_VMCS32_GUEST_DS_LIMIT   0x4806
#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS   0x4814
#define VMX_VMCS32_GUEST_ES_LIMIT   0x4800
#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS   0x481C
#define VMX_VMCS32_GUEST_FS_LIMIT   0x4808
#define VMX_VMCS32_GUEST_GDTR_LIMIT   0x4810
#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS   0x481E
#define VMX_VMCS32_GUEST_GS_LIMIT   0x480A
#define VMX_VMCS32_GUEST_IDTR_LIMIT   0x4812
#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE   0x4824
#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS   0x4820
#define VMX_VMCS32_GUEST_LDTR_LIMIT   0x480C
#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE   0x482E
#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS   0x4818
#define VMX_VMCS32_GUEST_SS_LIMIT   0x4804
#define VMX_VMCS32_GUEST_SYSENTER_CS   0x482A
#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS   0x4822
#define VMX_VMCS32_GUEST_TR_LIMIT   0x480E
VMCS field encoding - 32 Bits host state fields
#define VMX_VMCS32_HOST_SYSENTER_CS   0x4C00
VMCS field encoding - 32 Bits read-only fields
#define VMX_VMCS32_RO_EXIT_INSTR_INFO   0x440E
#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH   0x440C
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE   0x4406
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO   0x4404
#define VMX_VMCS32_RO_EXIT_REASON   0x4402
#define VMX_VMCS32_RO_IDT_ERRCODE   0x440A
#define VMX_VMCS32_RO_IDT_INFO   0x4408
#define VMX_VMCS32_RO_VM_INSTR_ERROR   0x4400
VMCS field encoding - Natural width guest state fields
#define VMX_VMCS64_GUEST_CR0   0x6800
#define VMX_VMCS64_GUEST_CR3   0x6802
#define VMX_VMCS64_GUEST_CR4   0x6804
#define VMX_VMCS64_GUEST_CS_BASE   0x6808
#define VMX_VMCS64_GUEST_DR7   0x681A
#define VMX_VMCS64_GUEST_DS_BASE   0x680C
#define VMX_VMCS64_GUEST_ES_BASE   0x6806
#define VMX_VMCS64_GUEST_FS_BASE   0x680E
#define VMX_VMCS64_GUEST_GDTR_BASE   0x6816
#define VMX_VMCS64_GUEST_GS_BASE   0x6810
#define VMX_VMCS64_GUEST_IDTR_BASE   0x6818
#define VMX_VMCS64_GUEST_LDTR_BASE   0x6812
#define VMX_VMCS64_GUEST_RIP   0x681E
#define VMX_VMCS64_GUEST_RSP   0x681C
#define VMX_VMCS64_GUEST_SS_BASE   0x680A
#define VMX_VMCS64_GUEST_SYSENTER_EIP   0x6826
#define VMX_VMCS64_GUEST_SYSENTER_ESP   0x6824
#define VMX_VMCS64_GUEST_TR_BASE   0x6814
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS   0x6822
#define VMX_VMCS_GUEST_RFLAGS   0x6820
VMCS field encoding - 64 Bits control fields
#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL   0x2014
#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH   0x2015
#define VMX_VMCS_CTRL_EPTP_FULL   0x201a
#define VMX_VMCS_CTRL_EPTP_HIGH   0x201b
#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL   0x200C
#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH   0x200D
#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL   0x2000
#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH   0x2001
#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL   0x2002
#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH   0x2003
#define VMX_VMCS_CTRL_MSR_BITMAP_FULL   0x2004
#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH   0x2005
#define VMX_VMCS_CTRL_TSC_OFFSET_FULL   0x2010
#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH   0x2011
#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL   0x2012
#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH   0x2013
#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL   0x200A
#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH   0x200B
#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL   0x2008
#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH   0x2009
#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL   0x2006
#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH   0x2007
#define VMX_VMCS_EXIT_PHYS_ADDR_FULL   0x2400
#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH   0x2401
Natural width control fields
#define VMX_VMCS_CTRL_CR0_MASK   0x6000
#define VMX_VMCS_CTRL_CR0_READ_SHADOW   0x6004
#define VMX_VMCS_CTRL_CR3_TARGET_VAL0   0x6008
#define VMX_VMCS_CTRL_CR3_TARGET_VAL1   0x600A
#define VMX_VMCS_CTRL_CR3_TARGET_VAL2   0x600C
#define VMX_VMCS_CTRL_CR3_TARGET_VAL31   0x600E
#define VMX_VMCS_CTRL_CR4_MASK   0x6002
#define VMX_VMCS_CTRL_CR4_READ_SHADOW   0x6006
VMCS field encoding - 32 Bits control fields
#define VMX_VMCS_CTRL_CR3_TARGET_COUNT   0x400A
#define VMX_VMCS_CTRL_ENTRY_CONTROLS   0x4012
#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE   0x4018
#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH   0x401A
#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO   0x4016
#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT   0x4014
#define VMX_VMCS_CTRL_EXCEPTION_BITMAP   0x4004
#define VMX_VMCS_CTRL_EXIT_CONTROLS   0x400C
#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT   0x4010
#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT   0x400E
#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK   0x4006
#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH   0x4008
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS   0x4000
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS   0x4002
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2   0x401E
#define VMX_VMCS_CTRL_TPR_THRESHOLD   0x401C
VMX_VMCS_CTRL_ENTRY_CONTROLS
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON   RT_BIT(11)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM   RT_BIT(10)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE   RT_BIT(9)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG   RT_BIT(2)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR   RT_BIT(15)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR   RT_BIT(14)
#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR   RT_BIT(13)
VMX_VMCS_CTRL_EXIT_CONTROLS
#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ   RT_BIT(15)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64   RT_BIT(9)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR   RT_BIT(21)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR   RT_BIT(19)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR   RT_BIT(12)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG   RT_BIT(2)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR   RT_BIT(20)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR   RT_BIT(18)
#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER   RT_BIT(22)
VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT   RT_BIT(0)
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT   RT_BIT(3)
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER   RT_BIT(6)
#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI   RT_BIT(5)
VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT   RT_BIT(2)
#define VMX_VMCS_CTRL_PROC_EXEC2_EPT   RT_BIT(1)
#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT   RT_BIT(10)
#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT   RT_BIT(3)
#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE   RT_BIT(7)
#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC   RT_BIT(0)
#define VMX_VMCS_CTRL_PROC_EXEC2_VPID   RT_BIT(5)
#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT   RT_BIT(6)
#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC   RT_BIT(4)
VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT   RT_BIT(15)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT   RT_BIT(16)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT   RT_BIT(19)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT   RT_BIT(20)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT   RT_BIT(7)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT   RT_BIT(9)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT   RT_BIT(2)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT   RT_BIT(29)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG   RT_BIT(27)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT   RT_BIT(23)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT   RT_BIT(10)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT   RT_BIT(22)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT   RT_BIT(30)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT   RT_BIT(11)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT   RT_BIT(12)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET   RT_BIT(3)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT   RT_BIT(24)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS   RT_BIT(25)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS   RT_BIT(28)
#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW   RT_BIT(21)
#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL   RT_BIT(31)
Natural width read-only data fields
#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR   0x640A
#define VMX_VMCS_RO_EXIT_QUALIFICATION   0x6400
#define VMX_VMCS_RO_IO_RCX   0x6402
#define VMX_VMCS_RO_IO_RDI   0x6406
#define VMX_VMCS_RO_IO_RIP   0x6408
#define VMX_VMCS_RO_IO_RSX   0x6404
VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0   RT_BIT(0)
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1   RT_BIT(1)
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2   RT_BIT(2)
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3   RT_BIT(3)
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED   RT_BIT(12)
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS   RT_BIT(14)
VMCS field encoding - 64 Bits guest fields
#define VMX_VMCS_GUEST_DEBUGCTL_FULL   0x2802
#define VMX_VMCS_GUEST_DEBUGCTL_HIGH   0x2803
#define VMX_VMCS_GUEST_EFER_FULL   0x2806
#define VMX_VMCS_GUEST_EFER_HIGH   0x2807
#define VMX_VMCS_GUEST_LINK_PTR_FULL   0x2800
#define VMX_VMCS_GUEST_LINK_PTR_HIGH   0x2801
#define VMX_VMCS_GUEST_PAT_FULL   0x2804
#define VMX_VMCS_GUEST_PAT_HIGH   0x2805
#define VMX_VMCS_GUEST_PDPTR0_FULL   0x280A
#define VMX_VMCS_GUEST_PDPTR0_HIGH   0x280B
#define VMX_VMCS_GUEST_PDPTR1_FULL   0x280C
#define VMX_VMCS_GUEST_PDPTR1_HIGH   0x280D
#define VMX_VMCS_GUEST_PDPTR2_FULL   0x280E
#define VMX_VMCS_GUEST_PDPTR2_HIGH   0x280F
#define VMX_VMCS_GUEST_PDPTR3_FULL   0x2810
#define VMX_VMCS_GUEST_PDPTR3_HIGH   0x2811
#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL   0x2808
#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH   0x2809
VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS   RT_BIT(1)
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI   RT_BIT(3)
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI   RT_BIT(2)
#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI   RT_BIT(0)
VMCS field encoding - Natural width host state fields
Bits 4-11, 13 and 15-63 are reserved.

#define VMX_VMCS_HOST_CR0   0x6C00
#define VMX_VMCS_HOST_CR3   0x6C02
#define VMX_VMCS_HOST_CR4   0x6C04
#define VMX_VMCS_HOST_FS_BASE   0x6C06
#define VMX_VMCS_HOST_GDTR_BASE   0x6C0C
#define VMX_VMCS_HOST_GS_BASE   0x6C08
#define VMX_VMCS_HOST_IDTR_BASE   0x6C0E
#define VMX_VMCS_HOST_RIP   0x6C16
#define VMX_VMCS_HOST_RSP   0x6C14
#define VMX_VMCS_HOST_SYSENTER_EIP   0x6C12
#define VMX_VMCS_HOST_SYSENTER_ESP   0x6C10
#define VMX_VMCS_HOST_TR_BASE   0x6C0A
VMCS field encoding - 64 bits host fields
#define VMX_VMCS_HOST_FIELD_EFER_FULL   0x2C02
#define VMX_VMCS_HOST_FIELD_EFER_HIGH   0x2C03
#define VMX_VMCS_HOST_FIELD_PAT_FULL   0x2C00
#define VMX_VMCS_HOST_FIELD_PAT_HIGH   0x2C01
#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL   0x2C04
#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH   0x2C05

Typedefs

MSR load/store elements
typedef const VMXMSR * PCVMXMSR
typedef VMXMSR * PVMXMSR

Functions

 DECLASM (int) VMXGetActivateVMCS(RTHCPHYS *pVMCS)
 DECLINLINE (void) VMXDisable(void)
 DECLINLINE (int) VMXEnable(RTHCPHYS pVMXOn)

Variables

uint64_t * pDescriptor


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