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Internals
[The Page Monitor / Manager API]


Detailed Description

For internal use only.


Classes

struct  PGM
struct  PGMCHUNKR3MAP
struct  PGMCHUNKR3MAPTLB
struct  PGMCHUNKR3MAPTLBE
struct  PGMCPU
struct  PGMMAPPING
struct  PGMMAPSET
struct  PGMMAPSETENTRY
struct  PGMMMIO2RANGE
struct  PGMMODEDATA
struct  PGMPAGE
struct  PGMPAGER3MAPTLB
struct  PGMPAGER3MAPTLBE
struct  PGMPHYS2VIRTHANDLER
struct  PGMPHYSCACHE
struct  PGMPHYSCACHEENTRY
struct  PGMPHYSHANDLER
struct  PGMPOOL
struct  PGMPOOLPAGE
struct  PGMPOOLPHYSEXT
struct  PGMPOOLUSER
struct  PGMRAMRANGE
struct  PGMROMPAGE
struct  PGMROMRANGE
struct  PGMTREES
struct  PGMVIRTHANDLER

Error injection.

bool PGM::afReserved [7]
bool volatile PGM::fErrInjHandyPages

PAE Guest Paging.

RTGCPHYS PGMCPU::aGCPhysGstPaePDs [4]
RTGCPHYS PGMCPU::aGCPhysGstPaePDsMonitored [4]
 PGMCPU::R0PTRTYPE (PX86PDPAE) apGstPaePDsR0[4]
 PGMCPU::R0PTRTYPE (PX86PDPT) pGstPaePdptR0
 PGMCPU::R3PTRTYPE (PX86PDPAE) apGstPaePDsR3[4]
 PGMCPU::R3PTRTYPE (PX86PDPT) pGstPaePdptR3
 PGMCPU::RCPTRTYPE (PX86PDPAE) apGstPaePDsRC[4]
 PGMCPU::RCPTRTYPE (PX86PDPT) pGstPaePdptRC

Release Statistics

uint32_t PGM::cAllPages
uint32_t PGM::cPrivatePages
STAMCOUNTER PGM::cRelocations
uint32_t PGM::cSharedPages
uint32_t PGM::cZeroPages

Intermediate Context

RTHCPHYS PGM::HCPhysInterPaePDPT
RTHCPHYS PGM::HCPhysInterPaePML4
RTHCPHYS PGM::HCPhysInterPD
 PGM::R3PTRTYPE (PX86PML4) pInterPaePML4
 PGM::R3PTRTYPE (PX86PDPT) pInterPaePDPT
 PGM::R3PTRTYPE (PX86PDPAE) apInterPaePDs[4]
 PGM::R3PTRTYPE (PX86PTPAE) apInterPaePTs[2]
 PGM::R3PTRTYPE (PX86PT) apInterPTs[2]
 PGM::R3PTRTYPE (PX86PD) pInterPD

The zero page.

RTHCPHYS PGM::HCPhysZeroPg
RTR0PTR PGM::pvZeroPgR0
RTR3PTR PGM::pvZeroPgR3
RTGCPTR PGM::pvZeroPgRC
uint32_t PGM::u32ZeroAlignment

Context neutrual page mapper TLB.

Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr code is writting in a kind of context neutrual way. Time will show whether this actually makes sense or not...

Todo:
this needs to be reconsidered and dropped/redone since the ring-0 context ends up using a global mapping cache on some platforms (darwin).


typedef PPGMCHUNKR3MAP PPGMPAGEMAP
typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB
typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE
typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP
typedef PPGMPAGER3MAPTLBEPPPGMPAGEMAPTLBE
#define PGM_PAGEMAPTLB_ENTRIES   PGM_PAGER3MAPTLB_ENTRIES
#define PGM_PAGEMAPTLB_IDX(GCPhys)   PGM_PAGER3MAPTLB_IDX(GCPhys)

Function pointers for Both Shadow and Guest paging.

 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthUnmapCR3,(PVMCPU pVCpu))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthUnmapCR3,(PVMCPU pVCpu))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthUnmapCR3,(PVMCPU pVCpu))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthSyncPage,(PVMCPU pVCpu, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault))

Function pointers for Guest paging.

 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3GstExit,(PVMCPU pVCpu))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys))

Function pointers for Shadow paging.

 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLR0CALLBACKMEMBER (int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3ShwExit,(PVMCPU pVCpu))
 PGMMODEDATA::DECLR3CALLBACKMEMBER (int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask))
 PGMMODEDATA::DECLRCCALLBACKMEMBER (int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys))

AMD64 Guest Paging.

 PGMCPU::R0PTRTYPE (PX86PML4) pGstAmd64Pml4R0
 PGMCPU::R3PTRTYPE (PX86PML4) pGstAmd64Pml4R3

32-bit Guest Paging.

 PGMCPU::R0PTRTYPE (PX86PD) pGst32BitPdR0
 PGMCPU::R3PTRTYPE (PX86PD) pGst32BitPdR3
 PGMCPU::RCPTRTYPE (PX86PD) pGst32BitPdRC

PGM Pool Indexes.

Aka. the unique shadow page identifier.

#define NIL_PGMPOOL_IDX   0
#define PGMPOOL_IDX_AMD64_CR3   3
#define PGMPOOL_IDX_FIRST   5
#define PGMPOOL_IDX_FIRST_SPECIAL   1
#define PGMPOOL_IDX_LAST   0x3fff
#define PGMPOOL_IDX_NESTED_ROOT   4
#define PGMPOOL_IDX_PD   1
#define PGMPOOL_IDX_PDPT   2

Paging mode macros

#define PGM_BTH_DECL(type, name)   PGM_CTX_DECL(type) PGM_BTH_NAME(name)
#define PGM_BTH_NAME_32BIT_32BIT(name)   PGM_CTX(pgm,Bth32Bit32Bit##name)
#define PGM_BTH_NAME_32BIT_PROT(name)   PGM_CTX(pgm,Bth32BitProt##name)
#define PGM_BTH_NAME_32BIT_REAL(name)   PGM_CTX(pgm,Bth32BitReal##name)
#define PGM_BTH_NAME_AMD64_AMD64(name)   PGM_CTX(pgm,BthAMD64AMD64##name)
#define PGM_BTH_NAME_AMD64_PROT(name)   PGM_CTX(pgm,BthAMD64Prot##name)
#define PGM_BTH_NAME_EPT_32BIT(name)   PGM_CTX(pgm,BthEPT32Bit##name)
#define PGM_BTH_NAME_EPT_AMD64(name)   PGM_CTX(pgm,BthEPTAMD64##name)
#define PGM_BTH_NAME_EPT_PAE(name)   PGM_CTX(pgm,BthEPTPAE##name)
#define PGM_BTH_NAME_EPT_PROT(name)   PGM_CTX(pgm,BthEPTProt##name)
#define PGM_BTH_NAME_EPT_REAL(name)   PGM_CTX(pgm,BthEPTReal##name)
#define PGM_BTH_NAME_NESTED_32BIT(name)   PGM_CTX(pgm,BthNested32Bit##name)
#define PGM_BTH_NAME_NESTED_AMD64(name)   PGM_CTX(pgm,BthNestedAMD64##name)
#define PGM_BTH_NAME_NESTED_PAE(name)   PGM_CTX(pgm,BthNestedPAE##name)
#define PGM_BTH_NAME_NESTED_PROT(name)   PGM_CTX(pgm,BthNestedProt##name)
#define PGM_BTH_NAME_NESTED_REAL(name)   PGM_CTX(pgm,BthNestedReal##name)
#define PGM_BTH_NAME_PAE_32BIT(name)   PGM_CTX(pgm,BthPAE32Bit##name)
#define PGM_BTH_NAME_PAE_PAE(name)   PGM_CTX(pgm,BthPAEPAE##name)
#define PGM_BTH_NAME_PAE_PROT(name)   PGM_CTX(pgm,BthPAEProt##name)
#define PGM_BTH_NAME_PAE_REAL(name)   PGM_CTX(pgm,BthPAEReal##name)
#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)   "pgmR0Bth32Bit32Bit" #name
#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name)   "pgmR0Bth32BitProt" #name
#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name)   "pgmR0Bth32BitReal" #name
#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)   "pgmR0BthAMD64AMD64" #name
#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name)   "pgmR0BthAMD64Prot" #name
#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name)   "pgmR0BthEPT32Bit" #name
#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name)   "pgmR0BthEPTAMD64" #name
#define PGM_BTH_NAME_R0_EPT_PAE_STR(name)   "pgmR0BthEPTPAE" #name
#define PGM_BTH_NAME_R0_EPT_PROT_STR(name)   "pgmR0BthEPTProt" #name
#define PGM_BTH_NAME_R0_EPT_REAL_STR(name)   "pgmR0BthEPTReal" #name
#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)   "pgmR0BthNested32Bit" #name
#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)   "pgmR0BthNestedAMD64" #name
#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name)   "pgmR0BthNestedPAE" #name
#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name)   "pgmR0BthNestedProt" #name
#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name)   "pgmR0BthNestedReal" #name
#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name)   "pgmR0BthPAE32Bit" #name
#define PGM_BTH_NAME_R0_PAE_PAE_STR(name)   "pgmR0BthPAEPAE" #name
#define PGM_BTH_NAME_R0_PAE_PROT_STR(name)   "pgmR0BthPAEProt" #name
#define PGM_BTH_NAME_R0_PAE_REAL_STR(name)   "pgmR0BthPAEReal" #name
#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)   "pgmRCBth32Bit32Bit" #name
#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name)   "pgmRCBth32BitProt" #name
#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name)   "pgmRCBth32BitReal" #name
#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)   "pgmRCBthAMD64AMD64" #name
#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name)   "pgmRCBthEPT32Bit" #name
#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name)   "pgmRCBthEPTAMD64" #name
#define PGM_BTH_NAME_RC_EPT_PAE_STR(name)   "pgmRCBthEPTPAE" #name
#define PGM_BTH_NAME_RC_EPT_PROT_STR(name)   "pgmRCBthEPTProt" #name
#define PGM_BTH_NAME_RC_EPT_REAL_STR(name)   "pgmRCBthEPTReal" #name
#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)   "pgmRCBthNested32Bit" #name
#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)   "pgmRCBthNestedAMD64" #name
#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name)   "pgmRCBthNestedPAE" #name
#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name)   "pgmRCBthNestedProt" #name
#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name)   "pgmRCBthNestedReal" #name
#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name)   "pgmRCBthPAE32Bit" #name
#define PGM_BTH_NAME_RC_PAE_PAE_STR(name)   "pgmRCBthPAEPAE" #name
#define PGM_BTH_NAME_RC_PAE_PROT_STR(name)   "pgmRCBthPAEProt" #name
#define PGM_BTH_NAME_RC_PAE_REAL_STR(name)   "pgmRCBthPAEReal" #name
#define PGM_BTH_PFN(name, pVCpu)   ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
#define PGM_CTX(a, b)   a##R0##b
#define PGM_CTX_DECL(type)   VMMDECL(type)
#define PGM_CTX_STR(a, b)   a "R0" b
#define PGM_GST_DECL(type, name)   PGM_CTX_DECL(type) PGM_GST_NAME(name)
#define PGM_GST_NAME_32BIT(name)   PGM_CTX(pgm,Gst32Bit##name)
#define PGM_GST_NAME_AMD64(name)   PGM_CTX(pgm,GstAMD64##name)
#define PGM_GST_NAME_PAE(name)   PGM_CTX(pgm,GstPAE##name)
#define PGM_GST_NAME_PROT(name)   PGM_CTX(pgm,GstProt##name)
#define PGM_GST_NAME_R0_32BIT_STR(name)   "pgmR0Gst32Bit" #name
#define PGM_GST_NAME_R0_AMD64_STR(name)   "pgmR0GstAMD64" #name
#define PGM_GST_NAME_R0_PAE_STR(name)   "pgmR0GstPAE" #name
#define PGM_GST_NAME_R0_PROT_STR(name)   "pgmR0GstProt" #name
#define PGM_GST_NAME_R0_REAL_STR(name)   "pgmR0GstReal" #name
#define PGM_GST_NAME_RC_32BIT_STR(name)   "pgmRCGst32Bit" #name
#define PGM_GST_NAME_RC_AMD64_STR(name)   "pgmRCGstAMD64" #name
#define PGM_GST_NAME_RC_PAE_STR(name)   "pgmRCGstPAE" #name
#define PGM_GST_NAME_RC_PROT_STR(name)   "pgmRCGstProt" #name
#define PGM_GST_NAME_RC_REAL_STR(name)   "pgmRCGstReal" #name
#define PGM_GST_NAME_REAL(name)   PGM_CTX(pgm,GstReal##name)
#define PGM_GST_PFN(name, pVCpu)   ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
#define PGM_SHW_DECL(type, name)   PGM_CTX_DECL(type) PGM_SHW_NAME(name)
#define PGM_SHW_NAME_32BIT(name)   PGM_CTX(pgm,Shw32Bit##name)
#define PGM_SHW_NAME_AMD64(name)   PGM_CTX(pgm,ShwAMD64##name)
#define PGM_SHW_NAME_EPT(name)   PGM_CTX(pgm,ShwEPT##name)
#define PGM_SHW_NAME_NESTED(name)   PGM_CTX(pgm,ShwNested##name)
#define PGM_SHW_NAME_PAE(name)   PGM_CTX(pgm,ShwPAE##name)
#define PGM_SHW_NAME_R0_32BIT_STR(name)   "pgmR0Shw32Bit" #name
#define PGM_SHW_NAME_R0_AMD64_STR(name)   "pgmR0ShwAMD64" #name
#define PGM_SHW_NAME_R0_EPT_STR(name)   "pgmR0ShwEPT" #name
#define PGM_SHW_NAME_R0_NESTED_STR(name)   "pgmR0ShwNested" #name
#define PGM_SHW_NAME_R0_PAE_STR(name)   "pgmR0ShwPAE" #name
#define PGM_SHW_NAME_RC_32BIT_STR(name)   "pgmRCShw32Bit" #name
#define PGM_SHW_NAME_RC_AMD64_STR(name)   "pgmRCShwAMD64" #name
#define PGM_SHW_NAME_RC_EPT_STR(name)   "pgmRCShwEPT" #name
#define PGM_SHW_NAME_RC_NESTED_STR(name)   "pgmRCShwNested" #name
#define PGM_SHW_NAME_RC_PAE_STR(name)   "pgmRCShwPAE" #name
#define PGM_SHW_PFN(name, pVCpu)   ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))

PGM Compile Time Config

#define PGM_MAX_PHYSCACHE_ENTRIES   64
#define PGM_MAX_PHYSCACHE_ENTRIES_MASK   (PGM_MAX_PHYSCACHE_ENTRIES-1)
#define PGM_OUT_OF_SYNC_IN_GC
#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
#define PGM_SYNC_N_PAGES
#define PGM_SYNC_NR_PAGES   8
#define PGMPOOL_CFG_MAX_GROW   (_256K >> PAGE_SHIFT)
#define PGMPOOL_WITH_CACHE
#define PGMPOOL_WITH_GCPHYS_TRACKING
#define PGMPOOL_WITH_MIXED_PT_CR3
#define PGMPOOL_WITH_MONITORING
#define PGMPOOL_WITH_USER_TRACKING

Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).

Remarks:
The values are assigned in order of priority, so we can calculate the correct state for a page with different handlers installed.


#define PGM_PAGE_HNDL_PHYS_STATE_ALL   3
#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED   1
#define PGM_PAGE_HNDL_PHYS_STATE_NONE   0
#define PGM_PAGE_HNDL_PHYS_STATE_WRITE   2

Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).

Remarks:
The values are assigned in order of priority, so we can calculate the correct state for a page with different handlers installed.


#define PGM_PAGE_HNDL_VIRT_STATE_ALL   3
#define PGM_PAGE_HNDL_VIRT_STATE_NONE   0
#define PGM_PAGE_HNDL_VIRT_STATE_WRITE   2

The Page state, PGMPAGE::u2StateX.

#define PGM_PAGE_STATE_ALLOCATED   1
#define PGM_PAGE_STATE_SHARED   3
#define PGM_PAGE_STATE_WRITE_MONITORED   2
#define PGM_PAGE_STATE_ZERO   0

Page directory flags.

These are placed in the three bits available for system programs in the page directory entries.

#define PGM_PDFLAGS_MAPPING   RT_BIT_64(10)
#define PGM_PDFLAGS_TRACK_DIRTY   RT_BIT_64(11)

PDPT and PML4 flags.

These are placed in the three bits available for system programs in the PDPT and PML4 entries.

#define PGM_PLXFLAGS_MAPPING   RT_BIT_64(11)
#define PGM_PLXFLAGS_PERMANENT   RT_BIT_64(10)

Page flags.

These are placed in the three bits available for system programs in the page entries.

#define PGM_PTFLAGS_CSAM_VALIDATED   RT_BIT_64(11)
#define PGM_PTFLAGS_TRACK_DIRTY   RT_BIT_64(9)

PGMRAMRANGE::fFlags

#define PGM_RAM_RANGE_FLAGS_FLOATING   RT_BIT(20)

PGM::fSyncFlags Flags

#define PGM_SYNC_ALWAYS   RT_BIT(1)
#define PGM_SYNC_CLEAR_PGM_POOL   RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
#define PGM_SYNC_CLEAR_PGM_POOL_BIT   8
#define PGM_SYNC_MAP_CR3   RT_BIT(3)
#define PGM_SYNC_MONITOR_CR3   RT_BIT(2)
#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL   RT_BIT(0)

Defines used to indicate the shadow and guest paging in the templates.

#define PGM_TYPE_32BIT   3
#define PGM_TYPE_AMD64   5
#define PGM_TYPE_EPT   7
#define PGM_TYPE_MAX   PGM_TYPE_EPT
#define PGM_TYPE_NESTED   6
#define PGM_TYPE_PAE   4
#define PGM_TYPE_PROT   2
#define PGM_TYPE_REAL   1

Page type predicates.

#define PGMPAGETYPE_IS_NP(type)   ( (type) == PGMPAGETYPE_MMIO )
#define PGMPAGETYPE_IS_READABLE(type)   ( (type) <= PGMPAGETYPE_ROM )
#define PGMPAGETYPE_IS_ROX(type)   ( (type) == PGMPAGETYPE_ROM )
#define PGMPAGETYPE_IS_RWX(type)   ( (type) <= PGMPAGETYPE_ROM_SHADOW )
#define PGMPAGETYPE_IS_WRITEABLE(type)   ( (type) <= PGMPAGETYPE_ROM_SHADOW )

Per guest page tracking data.

This is currently as a 16-bit word in the PGMPAGE structure, the idea though is to use more bits for it and split it up later on. But for now we'll play safe and change as little as possible.

The 16-bit word has two parts:

The first 14-bit forms the idx field. It is either the index of a page in the shadow page pool, or and index into the extent list.

The 2 topmost bits makes up the cRefs field, which counts the number of shadow page pool references to the page. If cRefs equals PGMPOOL_CREFS_PHYSEXT, then the idx field is an indext into the extent (misnomer) table and not the shadow page pool.

See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set the 16-bit word.

#define PGMPOOL_TD_CREFS_MASK   0x3
#define PGMPOOL_TD_CREFS_PHYSEXT   PGMPOOL_TD_CREFS_MASK
#define PGMPOOL_TD_CREFS_SHIFT   14
#define PGMPOOL_TD_GET_CREFS(u16)   ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
#define PGMPOOL_TD_GET_IDX(u16)   ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
#define PGMPOOL_TD_IDX_MASK   0x3fff
#define PGMPOOL_TD_IDX_OVERFLOWED   PGMPOOL_TD_IDX_MASK
#define PGMPOOL_TD_IDX_SHIFT   0
#define PGMPOOL_TD_MAKE(cRefs, idx)   ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )

Defines

#define NIL_PGMPOOL_PHYSEXT_INDEX   ((uint16_t)0xffff)
#define NIL_PGMPOOL_USER_INDEX   ((uint16_t)0xffff)
#define PGM2VM(pPGM)   ( (PVM)((char*)pPGM - pPGM->offVM) )
#define PGM_CHUNKR3MAPTLB_ENTRIES   32
#define PGM_CHUNKR3MAPTLB_IDX(idChunk)   ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv)   PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv))
#define PGM_GCPHYS_2_PTR_BY_PGMCPU(pPGM, GCPhys, ppv)   PGM_GCPHYS_2_PTR(PGMCPU2VM(pPGM), GCPhys, ppv)
#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv)   PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv))
#define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv)   MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
#define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv)   PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
#define PGM_INVL_ALL_VCPU_PG(pVM, GCVirt)   HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
#define PGM_INVL_ALL_VCPU_TLBS(pVM)   HWACCMFlushTLBOnAllVCpus(pVM)
#define PGM_INVL_BIG_PG(pVCpu, GCVirt)   HWACCMFlushTLB(pVCpu)
#define PGM_INVL_PG(pVCpu, GCVirt)   HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
#define PGM_INVL_VCPU_TLBS(pVCpu)   HWACCMFlushTLB(pVCpu)
#define PGM_PAGE_CLEAR(pPage)
#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage)   do { (pPage)->fWrittenToX = 0; } while (0)
#define PGM_PAGE_GET_CHUNKID(pPage)   ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
#define PGM_PAGE_GET_HCPHYS(pPage)   ( (pPage)->HCPhysX & UINT64_C(0x0000fffffffff000) )
#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)   ( (pPage)->u2HandlerPhysStateX )
#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)   ( (pPage)->u2HandlerVirtStateX )
#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage)   ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
#define PGM_PAGE_GET_PAGEID(pPage)   ( (pPage)->idPageX )
#define PGM_PAGE_GET_STATE(pPage)   ( (pPage)->u2StateX )
#define PGM_PAGE_GET_TD_CREFS(pPage)   ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
#define PGM_PAGE_GET_TD_IDX(pPage)   ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
#define PGM_PAGE_GET_TRACKING(pPage)   ( *((uint16_t *)&(pPage)->HCPhysX + 3) )
#define PGM_PAGE_GET_TYPE(pPage)   (pPage)->u3Type
#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)   ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage)   PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
#define PGM_PAGE_HAS_ANY_HANDLERS(pPage)
#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage)   ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)   ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState)
#define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType)   PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
#define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType)   PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
#define PGM_PAGE_IS_MMIO(pPage)   ( (pPage)->u3Type == PGMPAGETYPE_MMIO )
#define PGM_PAGE_IS_SHARED(pPage)   ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
#define PGM_PAGE_IS_WRITTEN_TO(pPage)   ( (pPage)->fWrittenToX )
#define PGM_PAGE_IS_ZERO(pPage)   ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys)
#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState)   do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState)   do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
#define PGM_PAGE_SET_PAGEID(pPage, _idPage)   do { (pPage)->idPageX = (_idPage); } while (0)
#define PGM_PAGE_SET_STATE(pPage, _uState)   do { (pPage)->u2StateX = (_uState); } while (0)
#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData)   do { *((uint16_t *)&(pPage)->HCPhysX + 3) = (u16TrackingData); } while (0)
#define PGM_PAGE_SET_TYPE(pPage, _enmType)   do { (pPage)->u3Type = (_enmType); } while (0)
#define PGM_PAGE_SET_WRITTEN_TO(pPage)   do { (pPage)->fWrittenToX = 1; } while (0)
#define PGM_PAGER3MAPTLB_ENTRIES   64
#define PGM_PAGER3MAPTLB_IDX(GCPhys)   ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
#define PGM_WITH_NX(uGstType, uShwType)
#define PGM_WITH_PAGING(uGstType, uShwType)
#define PGMCPU2PGM(pPGMCpu)   ( (PPGM)((char*)pPGMCpu - pPGMCpu->offPGM) )
#define PGMCPU2VM(pPGM)   ( (PVM)((char*)pPGM - pPGM->offVM) )
#define pgmHandlerVirtualDumpPhysPages(a)   do { } while (0)
#define PGMMAPPING_CONFLICT_MAX   8
#define PGMMAPSET_CLOSED   UINT32_C(0xdeadc0fe)
#define PGMMAPSET_HASH(HCPhys)   (((HCPhys) >> PAGE_SHIFT) & 127)
#define PGMMAPSET_MAX_FILL   (64U * 80U / 100U)
#define PGMPHYS2VIRTHANDLER_IN_TREE   RT_BIT(0)
#define PGMPHYS2VIRTHANDLER_IS_HEAD   RT_BIT(1)
#define PGMPHYS2VIRTHANDLER_OFF_MASK   (~(int32_t)3)
#define PGMPOOL_HASH(GCPhys)   ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
#define PGMPOOL_HASH_SIZE   0x40
#define PGMPOOL_PAGE_2_PTR(pVM, pPage)   ((pPage)->pvPageR3)
#define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage)   PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
#define PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPage)   PGMPOOL_PAGE_2_PTR(PGMCPU2VM(pPGM), pPage)

Typedefs

typedef const PGMPAGEPCPGMPAGE
typedef PGMPOOLPAGE const * PCPGMPOOLPAGE
typedef const PGMPOOLPHYSEXTPCPGMPOOLPHYSEXT
typedef const PGMPOOLUSERPCPGMPOOLUSER
typedef PGMPPGM
typedef struct PGMCHUNKR3MAPPPGMCHUNKR3MAP
typedef PGMCHUNKR3MAPTLBEPPGMCHUNKR3MAPTLBE
typedef PGMCPUPPGMCPU
typedef struct PGMMAPPINGPPGMMAPPING
typedef PGMMAPSETPPGMMAPSET
typedef PGMMAPSETENTRYPPGMMAPSETENTRY
typedef PGMMMIO2RANGEPPGMMMIO2RANGE
typedef struct PGMMODEDATAPPGMMODEDATA
typedef PGMPAGEPPGMPAGE
typedef PGMPAGER3MAPTLBPPGMPAGER3MAPTLB
typedef PGMPAGER3MAPTLBEPPGMPAGER3MAPTLBE
typedef PGMPHYS2VIRTHANDLERPPGMPHYS2VIRTHANDLER
typedef PGMPHYSHANDLERPPGMPHYSHANDLER
typedef struct PGMPOOLPPGMPOOL
typedef struct PGMPOOLPAGEPPGMPOOLPAGE
typedef struct PGMPOOLPHYSEXTPPGMPOOLPHYSEXT
typedef struct PGMPOOLUSERPPGMPOOLUSER
typedef PGMRAMRANGEPPGMRAMRANGE
typedef PGMROMPAGEPPGMROMPAGE
typedef PGMROMRANGEPPGMROMRANGE
typedef PGMTREESPPGMTREES
typedef PGMVIRTHANDLERPPGMVIRTHANDLER
typedef PPGMCHUNKR3MAPPPPGMCHUNKR3MAP
typedef PPGMPAGEPPPGMPAGE
typedef struct PGMPOOL ** PPPGMPOOL
typedef struct PGMPOOLPAGE ** PPPGMPOOLPAGE

Enumerations

enum  PGMPAGETYPE {
  PGMPAGETYPE_INVALID = 0, PGMPAGETYPE_RAM, PGMPAGETYPE_MMIO2, PGMPAGETYPE_MMIO2_ALIAS_MMIO,
  PGMPAGETYPE_ROM_SHADOW, PGMPAGETYPE_ROM, PGMPAGETYPE_MMIO, PGMPAGETYPE_END
}
enum  PGMPOOLACCESS {
  PGMPOOLACCESS_DONTCARE = 0, PGMPOOLACCESS_USER_RW, PGMPOOLACCESS_USER_R, PGMPOOLACCESS_USER_RW_NX,
  PGMPOOLACCESS_USER_R_NX, PGMPOOLACCESS_SUPERVISOR_RW, PGMPOOLACCESS_SUPERVISOR_R, PGMPOOLACCESS_SUPERVISOR_RW_NX,
  PGMPOOLACCESS_SUPERVISOR_R_NX
}
enum  PGMPOOLKIND {
  PGMPOOLKIND_INVALID = 0, PGMPOOLKIND_FREE, PGMPOOLKIND_32BIT_PT_FOR_PHYS, PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
  PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB, PGMPOOLKIND_PAE_PT_FOR_PHYS, PGMPOOLKIND_PAE_PT_FOR_32BIT_PT, PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
  PGMPOOLKIND_PAE_PT_FOR_PAE_PT, PGMPOOLKIND_PAE_PT_FOR_PAE_2MB, PGMPOOLKIND_32BIT_PD, PGMPOOLKIND_32BIT_PD_PHYS,
  PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD, PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD, PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD, PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
  PGMPOOLKIND_PAE_PD_FOR_PAE_PD, PGMPOOLKIND_PAE_PD_PHYS, PGMPOOLKIND_PAE_PDPT_FOR_32BIT, PGMPOOLKIND_PAE_PDPT,
  PGMPOOLKIND_PAE_PDPT_PHYS, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
  PGMPOOLKIND_64BIT_PD_FOR_PHYS, PGMPOOLKIND_64BIT_PML4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLKIND_EPT_PD_FOR_PHYS,
  PGMPOOLKIND_EPT_PT_FOR_PHYS, PGMPOOLKIND_ROOT_NESTED, PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
}

Functions

 AssertCompile (PGMPAGETYPE_END<=7)
 AssertCompileSize (PGMPAGE, 16)
 DECLCALLBACK (int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode
 DECLCALLBACK (void) pgmR3MapInfo(PVM pVM
RT_C_DECLS_END DECLINLINE (PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM
 DECLINLINE (int) pgmPoolAlloc(PVM pVM
PPGMMAPPING pgmGetMapping (PVM pVM, RTGCPTR GCPtr)
PX86PD pgmGstLazyMap32BitPD (PPGMCPU pPGM)
PX86PDPAE pgmGstLazyMapPaePD (PPGMCPU pPGM, uint32_t iPdpt)
PX86PDPT pgmGstLazyMapPaePDPT (PPGMCPU pPGM)
PX86PML4 pgmGstLazyMapPml4 (PPGMCPU pPGM)
bool pgmHandlerPhysicalIsAll (PVM pVM, RTGCPHYS GCPhys)
void pgmHandlerPhysicalResetAliasedPage (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage)
int pgmHandlerVirtualFindByPhysAddr (PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage)
RT_C_DECLS_BEGIN int pgmLock (PVM pVM)
int pgmMapActivateCR3 (PVM pVM, PPGMPOOLPAGE pShwPageCR3)
void pgmMapClearShadowPDEs (PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
int pgmMapDeactivateCR3 (PVM pVM, PPGMPOOLPAGE pShwPageCR3)
void pgmMapSetShadowPDEs (PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
int pgmPhysAllocPage (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
int pgmPhysGCPhys2CCPtrInternal (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
int pgmPhysGCPhys2CCPtrInternalReadOnly (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv)
int pgmPhysPageLoadIntoTlb (PPGM pPGM, RTGCPHYS GCPhys)
int pgmPhysPageLoadIntoTlbWithPage (PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys)
int pgmPhysPageMakeWritable (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
int pgmPhysPageMakeWritableUnlocked (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
int pgmPhysPageMap (PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv)
int pgmPhysPageMapByPageID (PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv)
int pgmPoolAllocEx (PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage=false)
void pgmPoolClearAll (PVM pVM)
int pgmPoolFlushPage (PPGMPOOL pPool, PPGMPOOLPAGE pPage)
void pgmPoolFlushPageByGCPhys (PVM pVM, RTGCPHYS GCPhys)
void pgmPoolFreeByPage (PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
PPGMPOOLPAGE pgmPoolGetPage (PPGMPOOL pPool, RTHCPHYS HCPhys)
void pgmPoolMonitorChainChanging (PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
int pgmPoolMonitorChainFlush (PPGMPOOL pPool, PPGMPOOLPAGE pPage)
void pgmPoolMonitorModifiedInsert (PPGMPOOL pPool, PPGMPOOLPAGE pPage)
int pgmPoolSyncCR3 (PVMCPU pVCpu)
int pgmPoolTrackFlushGCPhys (PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
uint16_t pgmPoolTrackPhysExtAddref (PVM pVM, uint16_t u16, uint16_t iShwPT)
void pgmPoolTrackPhysExtDerefGCPhys (PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
int pgmR3ExitShadowModeBeforePoolFlush (PVM pVM, PVMCPU pVCpu)
void pgmR3HandlerPhysicalUpdateAll (PVM pVM)
void pgmR3MapRelocate (PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping)
int pgmR3ReEnterShadowModeAfterPoolFlush (PVM pVM, PVMCPU pVCpu)
int pgmR3SyncPTResolveConflict (PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping)
int pgmR3SyncPTResolveConflictPAE (PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping)
int pgmShwGetEPTPDPtr (PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
int pgmShwSyncLongModePDPtr (PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
int pgmShwSyncPaePDPtr (PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
void pgmUnlock (PVM pVM)
 PGMCPU::R0PTRTYPE (PPGMPOOLPAGE) pShwPageCR3R0
 PGM::R0PTRTYPE (PPGMPOOL) pPoolR0
 PGM::R0PTRTYPE (PPGMMAPPING) pMappingsR0
 PGM::R0PTRTYPE (PPGMTREES) pTreesR0
 PGM::R0PTRTYPE (PPGMROMRANGE) pRomRangesR0
 PGM::R0PTRTYPE (PPGMRAMRANGE) pRamRangesR0
 PGMPOOL::R0PTRTYPE (PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0
 PGMPOOL::R0PTRTYPE (PPGMPOOLPHYSEXT) paPhysExtsR0
 PGMPOOL::R0PTRTYPE (PPGMPOOLUSER) paUsersR0
 PGMROMRANGE::R0PTRTYPE (struct PGMROMRANGE *) pNextR0
 PGMRAMRANGE::R0PTRTYPE (struct PGMRAMRANGE *) pNextR0
 PGMPHYSHANDLER::R0PTRTYPE (void *) pvUserR0
 PGMPHYSHANDLER::R0PTRTYPE (PFNPGMR0PHYSHANDLER) pfnHandlerR0
 PGMMAPPING::@742::R0PTRTYPE (PX86PTPAE) paPaePTsR0
 PGMMAPPING::@742::R0PTRTYPE (PX86PT) pPTR0
 PGMMAPPING::R0PTRTYPE (struct PGMMAPPING *) pNextR0
 PGMCPU::R3PTRTYPE (PPGMPOOLPAGE) pShwPageCR3R3
 PGM::@743::R3PTRTYPE (PAVLLU32NODECORE) pAgeTree
 PGM::R3PTRTYPE (PPGMPOOL) pPoolR3
 PGM::R3PTRTYPE (PPGMMODEDATA) paModeData
 PGM::R3PTRTYPE (PPGMMAPPING) pMappingsR3
 PGM::R3PTRTYPE (PPGMTREES) pTreesR3
 PGM::R3PTRTYPE (PPGMMMIO2RANGE) pMmio2RangesR3
 PGM::R3PTRTYPE (PPGMROMRANGE) pRomRangesR3
 PGM::R3PTRTYPE (PPGMRAMRANGE) pRamRangesR3
 PGMPOOL::R3PTRTYPE (const char *) pszAccessHandler
 PGMPOOL::R3PTRTYPE (PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3
 PGMPOOL::R3PTRTYPE (PPGMPOOLPHYSEXT) paPhysExtsR3
 PGMPOOL::R3PTRTYPE (PPGMPOOLUSER) paUsersR3
 PGMMMIO2RANGE::R3PTRTYPE (struct PGMMMIO2RANGE *) pNextR3
 PGMROMRANGE::R3PTRTYPE (const char *) pszDesc
 PGMROMRANGE::R3PTRTYPE (const void *) pvOriginal
 PGMRAMRANGE::R3PTRTYPE (const char *) pszDesc
 PGMRAMRANGE::R3PTRTYPE (void *) pvR3
 PGMRAMRANGE::R3PTRTYPE (struct PGMRAMRANGE *) pNextR3
 PGMVIRTHANDLER::R3PTRTYPE (const char *) pszDesc
 PGMVIRTHANDLER::R3PTRTYPE (PFNPGMR3VIRTHANDLER) pfnHandlerR3
 PGMVIRTHANDLER::R3PTRTYPE (PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3
 PGMPHYSHANDLER::R3PTRTYPE (const char *) pszDesc
 PGMPHYSHANDLER::R3PTRTYPE (void *) pvUserR3
 PGMPHYSHANDLER::R3PTRTYPE (PFNPGMR3PHYSHANDLER) pfnHandlerR3
 PGMMAPPING::@742::R3PTRTYPE (PX86PTPAE) paPaePTsR3
 PGMMAPPING::@742::R3PTRTYPE (PX86PT) pPTR3
 PGMMAPPING::R3PTRTYPE (const char *) pszDesc
 PGMMAPPING::R3PTRTYPE (void *) pvUser
 PGMMAPPING::R3PTRTYPE (PFNPGMRELOCATE) pfnRelocate
 PGMPOOLPAGE::R3R0PTRTYPE (void *) pvPageR3
 PGMPAGER3MAPTLBE::R3R0PTRTYPE (void *) volatile pv
 PGMPAGER3MAPTLBE::R3R0PTRTYPE (PPGMCHUNKR3MAP) volatile pMap
 PGMPAGER3MAPTLBE::R3R0PTRTYPE (PPGMPAGE) volatile pPage
 PGMCHUNKR3MAPTLBE::R3R0PTRTYPE (PPGMCHUNKR3MAP) volatile pChunk
 PGMCPU::RCPTRTYPE (PPGMPOOLPAGE) pShwPageCR3RC
 PGM::RCPTRTYPE (PPGMPOOL) pPoolRC
 PGM::RCPTRTYPE (uint8_t *) pbDynPageMapBaseGC
 PGM::RCPTRTYPE (PPGMMAPPING) pMappingsRC
 PGM::RCPTRTYPE (PPGMTREES) pTreesRC
 PGM::RCPTRTYPE (PPGMROMRANGE) pRomRangesRC
 PGM::RCPTRTYPE (PPGMRAMRANGE) pRamRangesRC
 PGM::RCPTRTYPE (PX86PTEPAE) paDynPageMapPaePTEsGC
 PGM::RCPTRTYPE (PX86PTE) paDynPageMap32BitPTEsGC
 PGMPOOL::RCPTRTYPE (PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC
 PGMPOOL::RCPTRTYPE (PPGMPOOLPHYSEXT) paPhysExtsRC
 PGMPOOL::RCPTRTYPE (PPGMPOOLUSER) paUsersRC
 PGMROMRANGE::RCPTRTYPE (struct PGMROMRANGE *) pNextRC
 PGMRAMRANGE::RCPTRTYPE (struct PGMRAMRANGE *) pNextRC
 PGMVIRTHANDLER::RCPTRTYPE (PFNPGMRCVIRTHANDLER) pfnHandlerRC
 PGMPHYSHANDLER::RCPTRTYPE (void *) pvUserRC
 PGMPHYSHANDLER::RCPTRTYPE (PFNPGMRCPHYSHANDLER) pfnHandlerRC
 PGMMAPPING::@742::RCPTRTYPE (PX86PTPAE) paPaePTsRC
 PGMMAPPING::@742::RCPTRTYPE (PX86PT) pPTRC
 PGMMAPPING::RCPTRTYPE (struct PGMMAPPING *) pNextRC
 VMMDECL (int) pgmPhysRomWriteHandler(PVM pVM

Variables

uint8_t PGMMMIO2RANGE::abAlignemnt [HC_ARCH_BITS==32?1:5]
PGMMAPSETENTRY PGMMAPSET::aEntries [64]
bool PGM::afAlignment0 [11]
RTGCPTR PGMMAPPING::aGCPtrConflicts [PGMMAPPING_CONFLICT_MAX]
AVLLU32NODECORE PGMCHUNKR3MAP::AgeCore
uint32_t   PGM::AgeingCountdown
GMMPAGEDESC PGM::aHandyPages [PGM_HANDY_PAGES]
RTHCPHYS PGM::aHCPhysDynPageMapCache [MM_HYPER_DYNAMIC_SIZE >>(PAGE_SHIFT+1)]
uint16_t PGMPOOLPHYSEXT::aidx [3]
uint16_t PGMPOOL::aiHash [PGMPOOL_HASH_SIZE]
uint8_t PGMMAPSET::aiHashTable [128]
RTRCPTR PGM::alignment4
uint32_t PGMPOOL::Alignment4
uint32_t PGM::aLockedDynPageMapCache [MM_HYPER_DYNAMIC_SIZE >>(PAGE_SHIFT)]
PGMPOOLPAGE PGMPOOL::aPages [PGMPOOL_IDX_FIRST]
PGMROMPAGE PGMROMRANGE::aPages [1]
PGMPAGE PGMRAMRANGE::aPages [1]
PGMPHYS2VIRTHANDLER PGMVIRTHANDLER::aPhysToVirt [HC_ARCH_BITS==32?1:2]
struct {
 R0PTRTYPE (PX86PTPAE) paPaePTsR0
 R0PTRTYPE (PX86PT) pPTR0
 R3PTRTYPE (PX86PTPAE) paPaePTsR3
 R3PTRTYPE (PX86PT) pPTR3
 RCPTRTYPE (PX86PTPAE) paPaePTsRC
 RCPTRTYPE (PX86PT) pPTRC
   RTHCPHYS   PGMMAPPING::HCPhysPaePT0
   RTHCPHYS   PGMMAPPING::HCPhysPaePT1
   RTHCPHYS   HCPhysPT
PGMMAPPING::aPTs [1]
uint32_t PGMROMRANGE::au32Alignemnt [HC_ARCH_BITS==32?7:3]
uint32_t PGMRAMRANGE::au32Alignment2 [HC_ARCH_BITS==32?2:1]
bool PGMPOOLPAGE::bPadding1
uint32_t PGMPOOLPAGE::bPadding2
uint32_t   PGM::c
RTGCPHYS PGMROMRANGE::cb
RTGCPHYS PGMRAMRANGE::cb
RTGCPTR PGMVIRTHANDLER::cb
RTGCPTR PGMMAPPING::cb
uint32_t PGM::cbMappingFixed
uint32_t PGMMAPPING::cConflicts
uint16_t PGMPOOL::cCurPages
uint32_t PGM::cHandyPages
struct {
 R3PTRTYPE (PAVLLU32NODECORE) pAgeTree
 R3R0PTRTYPE (PAVLU32NODECORE) pTree
   uint32_t   PGM::AgeingCountdown
   uint32_t   PGM::c
   uint32_t   PGM::cMax
   uint32_t   PGM::iNow
   PGMCHUNKR3MAPTLB   PGM::Tlb
PGM::ChunkR3Map
uint32_t PGMPOOLPAGE::cLocked
uint32_t   PGM::cMax
uint16_t PGMPOOL::cMaxPages
uint16_t PGMPOOL::cMaxPhysExts
uint16_t PGMPOOL::cMaxUsers
uint16_t PGMPOOLPAGE::cModifications
uint16_t PGMPOOL::cModifiedPages
uint32_t PGMVIRTHANDLER::cPages
uint32_t PGMPHYSHANDLER::cPages
uint32_t volatile PGMCHUNKR3MAP::cPermRefs
uint32_t PGMPOOL::cPresent
uint16_t PGMPOOLPAGE::cPresent
uint32_t PGMMAPPING::cPTs
uint16_t PGMMAPSETENTRY::cRefs
uint32_t volatile PGMCHUNKR3MAP::cRefs
PDMCRITSECT PGM::CritSect
uint16_t PGMPOOL::cUsedPages
uint8_t PGMPOOLPAGE::enmAccess
PGMMODE PGMCPU::enmGuestMode
SUPPAGINGMODE PGM::enmHostMode
RTGCPHYS PGMPOOLKIND enmKind
uint8_t PGMPOOLPAGE::enmKind
PGMROMPROT PGMROMPAGE::enmProt
PGMMODE PGMCPU::enmShadowMode
PGMVIRTHANDLERTYPE PGMVIRTHANDLER::enmType
PGMPHYSHANDLERTYPE PGMPHYSHANDLER::enmType
PGMPHYSCACHEENTRY PGMPHYSCACHE::Entry [PGM_MAX_PHYSCACHE_ENTRIES]
bool PGMCPU::fA20Enabled
bool PGMPOOLPAGE::fCached
bool PGMPOOL::fCacheEnabled
bool PGM::fDisableMappings
bool PGMMAPPING::fFinalized
bool PGM::fFinalizedMappings
uint32_t PGMROMRANGE::fFlags
uint32_t PGMRAMRANGE::fFlags
RTGCPHYS PGMPOOLKIND uint16_t
uint32_t PPPGMPOOLPAGE bool 
fLockPage
bool PGMMMIO2RANGE::fMapped
bool PGM::fMappingsFixed
bool PGMPOOLPAGE::fMonitored
bool PGM::fNoMorePhysWrites
bool PGMMMIO2RANGE::fOverlapping
bool PGM::fRamPreAlloc
bool volatile PGMPOOLPAGE::fReusedFlushPending
bool PGMPOOLPAGE::fSeenNonGlobal
uint32_t PGMPAGE::fSomethingElse: 1
RTUINT PGMCPU::fSyncFlags
uint32_t PGMPAGE::fWrittenToX: 1
bool PGMPOOLPAGE::fZeroed
RTGCPHYS GCPhys
RTGCPHYS PGMPOOLPAGE::GCPhys
RTGCPHYS PGMPHYSCACHEENTRY::GCPhys
RTGCPHYS PGMROMRANGE::GCPhys
RTGCPHYS PGM::GCPhys4MBPSEMask
RTGCPHYS PGMCPU::GCPhysA20Mask
RTGCPHYS PGMCPU::GCPhysCR3
RTGCUINT PCPUMCTXCORE RTGCPTR
RTGCPHYS 
GCPhysFault
RTGCPHYS PGMROMRANGE::GCPhysLast
RTGCPHYS PGMRAMRANGE::GCPhysLast
RTGCPTR PGMMAPPING::GCPtr
RTRCPTR PGMROMRANGE::GCPtrAlignment
RTGCPTR PGM::GCPtrCR3Mapping
RTGCPTR PGMMAPPING::GCPtrLast
RTGCPTR PGM::GCPtrMappingFixed
RTRCPTR PGM::GCPtrPadding2
RTGCPTR PGM::GCPtrPrevRamRangeMapping
RTHCPHYS PGMMAPSETENTRY::HCPhys
RTHCPHYS   PGMMAPPING::HCPhysPaePT0
RTHCPHYS   PGMMAPPING::HCPhysPaePT1
AVLOHCPHYSTREE PGMPOOL::HCPhysTree
AVLROGCPTRTREE PGMTREES::HyperVirtHandlers
uint32_t PGMCHUNKR3MAP::iAge
uint16_t PGMPOOL::iAgeHead
uint16_t PGMPOOLPAGE::iAgeNext
uint16_t PGMPOOLPAGE::iAgePrev
uint16_t PGMPOOL::iAgeTail
int32_t PGMMAPSET::iCpu
uint32_t PGMPAGE::idPageX: 28
uint16_t PGMPOOLPAGE::idx
RTUINT PGM::iDynPageMapLast
uint16_t PGMPOOLPAGE::iFirstPresent
uint16_t PGMPOOL::iFreeHead
uint16_t PGMPOOL::iModifiedHead
uint16_t PGMPOOLPAGE::iModifiedNext
uint16_t PGMPOOLPAGE::iModifiedPrev
uint16_t PGMPOOLPAGE::iMonitoredNext
uint16_t PGMPOOLPAGE::iMonitoredPrev
uint16_t PGMPOOLPAGE::iNext
uint32_t   PGM::iNow
uint16_t PGMPOOL::iPhysExtFreeHead
uint8_t PGMMMIO2RANGE::iRegion
uint32_t PGMCPU::iShwUser
uint32_t PGMCPU::iShwUserTable
uint32_t PGMMAPSET::iSubset
RTGCPHYS PGMPOOLKIND uint16_t iUser
uint16_t PGMPOOLUSER::iUser
uint16_t PGMPOOL::iUserFreeHead
uint16_t PGMPOOLPAGE::iUserHead
RTGCPHYS PGMPOOLKIND uint16_t
uint32_t 
iUserTable
uint32_t PGMPOOLUSER::iUserTable
int32_t PGMPHYS2VIRTHANDLER::offNextAlias
RTINT PGMCPU::offPGM
RTINT PGMCPU::offVCpu
RTINT PGM::offVCpuPGM
int32_t PGMPHYS2VIRTHANDLER::offVirtHandler
PCDBGFINFOHLP pHlp
PGMPAGER3MAPTLB PGM::PhysTlbHC
AVLROGCPHYSTREE PGMTREES::PhysToVirtHandlers
RTGCPHYS PGMPOOLKIND uint16_t
uint32_t PPPGMPOOLPAGE 
ppPage
RTGCUINT PCPUMCTXCORE pRegFrame
PCDBGFINFOHLP const char * pszArgs
void * PGMCHUNKR3MAP::pv
RTGCUINT PCPUMCTXCORE RTGCPTR pvFault
PVMR0 PGMPOOL::pVMR0
PVMRC PGMPOOL::pVMRC
RTR0PTR PGMMAPSETENTRY::pvPage
RTR0PTR PGM::pvR0DynMapUsed
RTR3PTR PGMMMIO2RANGE::pvR3
void * pvUser
PGMRAMRANGE PGMMMIO2RANGE::RamRange
PGMPAGE PGMROMPAGE::Shadow
PGMCHUNKR3MAPTLB   PGM::Tlb
uint16_t PGMPOOL::u16Padding
uint32_t PGMPAGE::u29B: 25
uint32_t PGMPAGE::u2HandlerPhysStateX: 2
uint32_t PGMPAGE::u2HandlerVirtStateX: 2
uint32_t PGMPAGE::u2StateX: 2
uint32_t PGMROMPAGE::u32Padding
uint32_t PGMPAGE::u3Type: 3
RTGCUINT uErrorCode
RTINT PGMCPU::uPadding0
uint32_t PGMMODEDATA::uShwType
AVLROGCPTRTREE PGMTREES::VirtHandlers


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