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Sourcecode: virtualbox-ose version File versions

EMDECL ( int   ) 

Disassembles one instruction.

Parameters:
pVM The VM handle.
pCtxCore The context core (used for both the mode and instruction).
pCpu Where to return the parsed instruction info.
pcbInstr Where to return the instruction size. (optional)
Disassembles one instruction.

This is used by internally by the interpreter and by trap/access handlers.

Parameters:
pVM The VM handle.
GCPtrInstr The flat address of the instruction.
pCtxCore The context core (used to determin the cpu mode).
pCpu Where to return the parsed instruction info.
pcbInstr Where to return the instruction size. (optional)
Interprets the current instruction.

Returns:
VBox status code.
Return values:
VINF_* Scheduling instructions.
VERR_EM_INTERPRETER Something we can't cope with.
VERR_* Fatal errors.
Parameters:
pVM The VM handle.
pRegFrame The register frame. Updates the EIP if an instruction was executed successfully.
pvFault The fault address (CR2).
pcbSize Size of the write (if applicable).
Remarks:
Invalid opcode exceptions have a higher priority than GP (see Intel Architecture System Developers Manual, Vol 3, 5.5) so we don't need to worry about e.g. invalid modrm combinations (!)
Interprets the current instruction using the supplied DISCPUSTATE structure.

EIP is *NOT* updated!

Returns:
VBox status code.
Return values:
VINF_* Scheduling instructions. When these are returned, it starts to get a bit tricky to know whether code was executed or not... We'll address this when it becomes a problem.
VERR_EM_INTERPRETER Something we can't cope with.
VERR_* Fatal errors.
Parameters:
pVM The VM handle.
pCpu The disassembler cpu state for the instruction to be interpreted.
pRegFrame The register frame. EIP is *NOT* changed!
pvFault The fault address (CR2).
pcbSize Size of the write (if applicable).
Remarks:
Invalid opcode exceptions have a higher priority than GP (see Intel Architecture System Developers Manual, Vol 3, 5.5) so we don't need to worry about e.g. invalid modrm combinations (!)
Interpret CPUID given the parameters in the CPU context

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
Interpret RDTSC

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
Interpret INVLPG

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
pAddrGC Operand address
Interpret IRET (currently only to V86 code)

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
Interpret DRx write

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
DestRegDRx DRx register index (USE_REG_DR*)
SrcRegGen General purpose register index (USE_REG_E**))
Interpret DRx read

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
DestRegGen General purpose register index (USE_REG_E**))
SrcRegDRx DRx register index (USE_REG_DR*)
Interpret CRx write

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
DestRegCRx DRx register index (USE_REG_CR*)
SrcRegGen General purpose register index (USE_REG_E**))
Interpret CRx read

Returns:
VBox status code.
Parameters:
pVM The VM handle.
pRegFrame The register frame.
DestRegGen General purpose register index (USE_REG_E**))
SrcRegCRx CRx register index (USE_REG_CR*)
Interpret LMSW

Returns:
VBox status code.
Parameters:
pVM The VM handle.
u16Data LMSW source data.
Interpret CLTS

Returns:
VBox status code.
Parameters:
pVM The VM handle.
Interpret a port I/O instruction.

Returns:
VBox status code suitable for scheduling.
Parameters:
pVM The VM handle.
pCtxCore The context core. This will be updated on successful return.
pCpu The instruction to interpret.
cbOp The size of the instruction.
Remarks:
This may raise exceptions.


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